| ??? 12/05/12 01:49 Read: times |
#188965 - They don't know it either... Responding to: ???'s previous message |
Richard said:
I believe that you, Kai, once pointed out that there might have been oscillator startup issues that required the long-time-constant in the RESET circuit that Intel originally recommended. Yes, it was me, I remember. Richard said:
I find it unpleasant that on not-so-rare occasion, the MCU runs on during active RESET, once the Vdd is well below specified limits, but still high enough to cause problems,... I'm absolutely sure that some micros do exactly that. And if they do so during power down, there are two critical moments: The first moment is the ill running of micro at supply voltages, when the charge pump of programming voltage can still produce dangerous levels resulting in a corruption of flash memory. The second moment is, when the supply voltage rises up again to the nominal voltage WITHOUT giving the POR or BOR, call it like you want, the chance to properly reset the micro. This can happen, if the supply voltage does not actually fall down to 0V or at least under the specified threshold, if any is given in the datasheet. For the P89LP9211 this threshold (VPOR) is 0,5V by the way. So, from this above, for me it's essential to have Vcc actually going down to 0V between a power down and the next power up. This is why I think that a control of power up slope rate is important when working with modern microcntrollers having a flash code memory and this internal POR and BOR stuff. Richard said:
It's safe minimal limits on the rise and fall of Vdd that I'm seeking, however, and not just recommendations. From the fact, that manufacturers never didn't state anything precise about this topic in their datasheets, from the fact that they still recommended this stupid RC-reset circuit even many years after the first reports on flash code memory corruptions due to improper resets, from the fact that they still give completely glueless explanation how their PORs and BORs work, I come to the realization that they do not have safe limits at all. Jim said:
(dV/dt)r rise rate of VDD; to ensure power-on reset signal 5 - 5000 V/S
(dV/dt)f fall rate of VDD - - 50 mV/usec VPOR power-on reset voltage - - 0.5 V Yes, that's the same what I have found in the datasheet of http://www.nxp.com/documents...PC92X1.pdf The fall rate specification is similar to that of older reset controllers, like the DS1232, by the way: http://datasheets.maximintegrated.com/en/ds/DS1...DS1232.pdf Jim said:
That VPOR spec I guess is without the BrownOut detector operating ? That's exactly the point: Why would you need a POR when you have a working BOR?? I think, that the BOR is NOT working at the begin of power up. The POR seems to be needed to do some sort of initialisation, like resetting some flip flops or else. There seems to be a vulnerable time window at power up, the period between activated POR and inactivated BOR. Or by other words: There's no working BOR without a proper POR phase. The perfect power-up probably looks like that: At the beginning Vcc is at 0V. Afterwards Vcc monotonically rises with a slope rate specified in datasheet to its nominal value, without downs, dips, fluctuations, relevant noise, etc. In the mean time the micro, hopefully, has had enough time to activate the BOR, so that following undervoltage situations like dips and power downs can be responded by a proper reset. During a power down, on the other hand, Vcc must fall sufficiently slowly so that the BOR can trip a reset. After each power down Vcc must fall down to 0V. Kai Klaas |
