This is kind of off-topic, but it is for a legacy 8051 circuit. Consider an SRAM circuit like 6116 or 6264 that is battery-backed, and has working circuits for data retention, reset, WE*, etc. I want to make an SRAM 2x or 4x that is bank-switched with a hardware switch (SPST, SPDT). The SRAM is socketed so, no, I don't have to piggy-back stack them. ;-) I can make a board. The unit will be "off" when the bank switch occurs, so it's a simple A:B thing.

All I have to do is manage the highest order address line Axx via the switch. My concern is current drain when the unit is powered off and VMEM retains the memory. All other lines are paralleled. "VMEM" is the battery voltage when power is off and 5vDC when the unit is turned on. Not sure what else to call it, but it's what is hooked to Vcc on the SRAM. This is already handled in the legacy unit. Couple of diodes kind of thing.

With a TTL input I could leave the Axx line open ("floats" high to VBAT) for one bank and bring it low with something like 2k2 for the other. Easy enough with one SPST and one resistor. Lots of current though, right? With these CMOS SRAMs is a pullup to VMEM better? Or tie it directly there? And also a weaker pulldown? Like 10k? I'm not sure how to determine what draws the least amount of current and still gets the logic solid.

                  .------U-------
Vmem---o----------| Vcc
       |          |  
       |          |  
       <          |  
       < R1?      |  
       <          |  
       |   SPDT   |  
         /--------| Axx (highest addr line)
       |          |  
       |          |  
       <          |  
       < R2?      |  
       <
       |
       |
      ===  GND
       =


 

Sorry, I don't have a schematic handy, but I can google for one later or cobble something together.